DK-DEV-5SGXEA7N【PDF 212/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

您好，
买卖IC网欢迎您。
请登录
免费注册

208页 209页 210页 211页 [212页]213页 214页 215页 216页

SV51008

2014.01.10

DQS Postamble Circuitry

7-21

There are four delay elements in the DQS delay chain that have the same characteristics:

? Delay elements in the DQS logic block

? Delay elements in the DLL

The first delay chain closest to the DQS/CQ pin is shifted either by the DQS delay settings or by the sum of

the DQS delay setting and the phase-offset setting. The DQS delay settings can come from the DQS phase-

shift circuitry on either end of the I/O banks or from the logic array.

The number of delay chains required is transparent because the UniPHY IP automatically sets it when you

choose the operating frequency.

In Stratix V devices, if you do not use the DLL to control the DQS delay chains, you can input your own

gray-coded 7 bit settings using the delayctrlin[6..0] signals available in the UniPHY IP. These settings

control 1, 2, 3, or all 4 delay elements in the DQS delay chains. The UniPHY megafunction can also

dynamically choose the number of DQS delay chains required for the system. The amount of delay is equal

to the sum of the intrinsic delay of the delay element and the product of the number of delay steps and the

value of the delay steps. You can also bypass the DQS delay chain to achieve a 0° phase shift.

Related Information

? ALTDQ_DQS2 Megafunction User Guide

Provides more information about programming the delay chains.

? Delay Chains on page 7-26

DQS Postamble Circuitry

There are preamble and postamble specifications for both read and write operations in DDR3 and DDR2

SDRAM. The DQS postamble circuitry ensures that data is not lost if there is noise on the DQS line during

the end of a read operation that occurs while DQS is in a postamble state.

The Stratix V devices contain dedicated postamble registers that you can control to ground the shifted DQS

signal that is used to clock the DQ input registers at the end of a read operation. This function ensures that

any glitches on the DQS input signal during the end of a read operation and occurring while DQS is in a

postamble state do not affect the DQ IOE registers.

? For preamble state, the DQS is low, just after a high-impedance state.

? For postamble state, the DQS is low, just before it returns to a high-impedance state.

For external memory interfaces that use a bidirectional read strobe (DDR3 and DDR2 SDRAM), the DQS

signal is low before going to or coming from a high-impedance state.

Half Data Rate Block

The Stratix V devices contain a half data rate (HDR) block in the postamble enable circuitry.

The HDR block is clocked by the half-rate resynchronization clock, which is the output of the I/O clock

divider circuit. There is an AND gate after the postamble register outputs to avoid postamble glitches from

a previous read burst on a non-consecutive read burst. This scheme allows half-a-clock cycle latency for

dqsenable assertion and zero latency for dqsenable deassertion.

Using the HDR block as the first stage capture register in the postamble enable circuitry block is optional.

Altera recommends using these registers if the controller is running at half the frequency of the I/Os.

External Memory Interfaces in Stratix V Devices

Send Feedback

Altera Corporation

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

我的联系方式

*

*

*

相关PDF资料

DK-DSP-2S180N DSP PRO KIT W/SII EP2S180N

DK-DSP-3C120N KIT DEV DSP CYCLONE III EDITION

DK-K7-CONN-CES-G KINTEX-7 FPGA CONNECTIVITY KIT

DK-K7-EMBD-CES-G-J KINTEX-7 FPGA EMBEDDED KIT JAPAN

DK-MAXII-1270N KIT DEV MAXII W/EPM 1270N

DK-N2EVAL-3C25N KIT DEV NIOS II CYCLONE III ED.

DK-NIOS-2C35N NIOS II KIT W/CYCLONE II EP2C35N

DK-NIOS-2S60N NIOS II KIT W/STRATIX II EP2S60N

相关代理商/技术参数

DK-DSP-2C70N 功能描述:DSP KIT W/CYCLONE II EPS2C70N RoHS:是类别:编程器，开发系统 >> 通用嵌入式开发板和套件（MCU、DSP、FPGA、CPLD等）系列:Cyclone® II 产品培训模块:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色产品:Blackfin? BF50x Series Processors 标准包装:1 系列:Blackfin® 类型:DSP 适用于相关产品:ADSP-BF548 所含物品:板，软件，4x4 键盘，光学拨轮，QVGA 触摸屏 LCD 和 40G 硬盘配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相关产品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA

DK-DSP-2S180N 功能描述:DSP PRO KIT W/SII EP2S180N RoHS:是类别:编程器，开发系统 >> 通用嵌入式开发板和套件（MCU、DSP、FPGA、CPLD等）系列:Stratix® II 产品培训模块:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色产品:Blackfin? BF50x Series Processors 标准包装:1 系列:Blackfin® 类型:DSP 适用于相关产品:ADSP-BF548 所含物品:板，软件，4x4 键盘，光学拨轮，QVGA 触摸屏 LCD 和 40G 硬盘配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相关产品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA

DK-DSP-2S60N 功能描述:DSP KIT W/STRATIX II EP2S60N RoHS:是类别:编程器，开发系统 >> 通用嵌入式开发板和套件（MCU、DSP、FPGA、CPLD等）系列:Stratix® II 产品培训模块:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色产品:Blackfin? BF50x Series Processors 标准包装:1 系列:Blackfin® 类型:DSP 适用于相关产品:ADSP-BF548 所含物品:板，软件，4x4 键盘，光学拨轮，QVGA 触摸屏 LCD 和 40G 硬盘配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相关产品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA

DK-DSP-3C120N 功能描述:可编程逻辑 IC 开发工具 FPGA Development Kit For EP3C120F780 RoHS:否制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压:

DK-DSP-3SL150N 功能描述:可编程逻辑 IC 开发工具 FPGA Development Kit For EP3SL150F1152 RoHS:否制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压:

DK-DTK-120HW 制造商:FLORIDA MISC. 功能描述:

DKE10 制造商:MEANWELL 制造商全称:Mean Well Enterprises Co., Ltd. 功能描述:10W DC-DC Regulated Dual Output Converter

DKE10A-05 功能描述:DC/DC转换器 9-18Vin +/-5Vout 100-1000mA, 10W RoHS:否制造商:Murata 产品: 输出功率: 输入电压范围:3.6 V to 5.5 V 输入电压（标称）: 输出端数量:1 输出电压（通道 1）:3.3 V 输出电流（通道 1）:600 mA 输出电压（通道 2）: 输出电流（通道 2）: 安装风格:SMD/SMT 封装 / 箱体尺寸: